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This paper considers the problem of lookup table (LUT) based FPGA technology mapping for power minimization in combinational circuits. The problem has been previously proved to be NP-hard, and hence we present an efficient heuristic algorithm, PowerMap_er. This paper describes a technique that reduces power consumption by reducing the edge count in mapped network. The purpose of this technique is...
Thermal crisis has been widely regarded by IC industry. High temperature heavily impacts on reliability, performance, cooling cost and power consumption of ICs. High temperature can be reduced by increasing area. However arbitrarily large area, namely high number of resources in high-level view, dramatically increases IC cost. This paper proposes a technique to achieve proper thermal-area tradeoff...
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