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A multiple-valued reconfigurable VLSI based on logic-in-control architecture is proposed to make interconnections between arithmetic/logic circuits and control circuits simple. Hybrid programming scheme based on wired programming and dynamic data-path control programming is introduced to achieve high utilization ratio of hardware resources. In logic-in-control architecture, the control circuit constructed...
Damage-less full molecular-pore-stack SiOCH (MPS) / Cu interconnect is developed to reduce effective k-value (keff). MPS with high endurance against plasma processes is introduced into both via and trench dielectrics without hard mask (HM). Low friction slurry and chemical modification of MPS surface by He-plasma treatment suppress defect generation during direct CMP of the MPS surface. The full-MPS...
A fine-grain reconfigurable VLSI for various applications including arithmetic operations is developed. In the fine-grain architecture, it is important to define a cell function which leads to high utilization of a logic block and reduction of a switch block. From the point of view, a universal-literal-based multiple-valued cell suitable for bit- serial reconfigurable computation is proposed. One...
We have investigated micro-void formation mechanism in vias at 45 nm-node using OBIRCH method and SEM analysis, and found that micro-void formation is induced by via contour distortion. We have also clarified the correlation between edge roughness of a via pattern and micro-void formation. From this, we conclude that via edge roughness suppression is the key technology for robust interconnects fabrication...
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