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This work presents the co-integration of resistive random access memory crossbars within a 180 nm Read-Write CMOS chip. -based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of-the-Line. Two different strategies, consisting in insertion of an tunnel barrier layer and the design of a dedicated...
This work reports a technique to fabricate ReRAM crossbar arrays co-integrated with fully finished 180nm CMOS technology chips. The proposed integration method enables low-cost ReRAM-CMOS integration and allows the rapid prototyping of complete memory systems. We propose to use W plugs, already present as vias in CMOS technology, as the ReRAM bottom electrodes. The resistance switching layer, WOx,...
In this paper we present the design of a programmable frequency divider in 28 nm FD-SOI CMOS technology. It consists of the cascade of a divide-by-2 cell and divide-by-2/3 blocks. The final circuit is capable of dividing by even numbers between 128 and 254. The forward-body-bias property of the process and the differential-cascode voltage-switch-logic (DCVSL) family are used to achieve high operation...
This paper presents a read-write design solution for passive ReRAM crossbar memory arrays to overcome the sneak current paths problem. The proposed circuitry includes an auto-calibration feature to overcome the sneak current effects during the READ operation, and a WRITE protocol to minimize the current at each row and column lines. The presented circuit has been designed in 180nm standard CMOS technology...
An asynchronous 8× interleaved redundant SAR ADC achieving 8.8GS/s at 35mWand 1V supply is presented. The ADC features pass-gate selection clocking scheme for time-skew minimization and per-channel gain control based on low-power reference voltage buffers. The sub-ADC stacks the capacitive SAR DAC (CDAC) with the reference capacitor to reduce the area and enhance the settling speed. It achieves 38...
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