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As the number of processing elements increases in a single chip, the interconnect backbone becomes more and more stressed when serving frequent memory and cache accesses. Network-on-Chip (NoC) has emerged as a potential solution to provide a flexible and scalable interconnect in a planar platform. In the mean time, three-dimensional (3D) integration technology pushes circuit design beyond Moore's...
To solve the problems of congestion and fault tolerance for global communication management in network on chip (NoC), a novel dynamic routing scheme base on network monitor called DyRS-NM, is proposed for NoC application. DyRS-NM has the ability to locate dynamic congested or faulty links to detour them based on the overall network status values collected by network monitor, and also can balance the...
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