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An efficient turbo decoder must access memory in parallel and with two different access patterns. It is shown that the problem of accessing memory both with sequential and interleaved access patterns is analogous to the graph coloring problem. The derivation proves that the obtained graph is bipartite and, therefore, only two memory banks are required in theory. For practical implementations, a system...
Advanced Encryption Standard (AES) algorithm incorporates a byte permutation operation which reorders the bytes within a 128-bit data block. This permutation can be described by reading the input data bytes into a 4×4 matrix called state in column wise and shifting the rows by one, two, or three bytes to the left. In decryption, the shifting is reversed, i.e., the rows are shifted to the right. While...
In the area of Embedded Systems, instruction memories are one of the critical components consuming significant amounts of energy. Existence of a relation between size of the compiled program, and consequently required size of the instruction memory, and the compiler optimization flags is well-known. In particular, loop transformations such as loop unrolling, while having potential to increase performance...
In this work, we present a minimalistic, energy efficient implementation of instruction buffer. We use loop detection and execution trace analysis to find most commonly executed loops in already scheduled application and tailor instruction buffer size to the size of most commonly executed loop(s). In addition to our previous work, we allow buffering of loops with limited control flow (early exit from...
FFT algorithms are inherently highly parallel and often require frequent access to memory indicating need for high memory bandwidth. Unfortunately, in-place FFT algorithms access data in specific data patterns, thus conflict-free parallel access calls for specialized access schemes. In this paper, we propose a conflict-free parallel access scheme for mixed-radix FFT computations, which supports not...
Use of Instruction Buffers (also named Repeat Buffers), and caches is common way to avoid memory speed bottleneck in presence of memory hierarchies. Once the instruction resides in a cache or a buffer, repeated execution of the same instruction does not require separate memory access and possible cache miss. Use of the instruction buffers offer also an advantage when low energy consumption is an issue...
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