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This paper presents area-efficient building blocks for computing fast Fourier transform (FFT): multiplierless processing elements to be used for computing of radix-3 and radix-5 butterflies and reconfigurable processing element supporting mixed radix-2/3/4/5 FFT algorithms. The proposed processing elements are based on Wingorad Fourier transform algorithm. However, multiplication is performed by constant...
FFT algorithms are inherently highly parallel and often require frequent access to memory indicating need for high memory bandwidth. Unfortunately, in-place FFT algorithms access data in specific data patterns, thus conflict-free parallel access calls for specialized access schemes. In this paper, we propose a conflict-free parallel access scheme for mixed-radix FFT computations, which supports not...
Use of Instruction Buffers (also named Repeat Buffers), and caches is common way to avoid memory speed bottleneck in presence of memory hierarchies. Once the instruction resides in a cache or a buffer, repeated execution of the same instruction does not require separate memory access and possible cache miss. Use of the instruction buffers offer also an advantage when low energy consumption is an issue...
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