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The recent emergence of direct sampling in residential broadband satellite and cable receivers has spurred the need for low-power, high-speed (∼5GS/s), mid-resolution (∼10b) A/D converters. Recently, time-interleaved (TI) SARs have been a popular choice for low-power, medium-speed, mid-resolution ADCs [1-3]. As the conversion rate and resolution requirements increase, TI-SARs become less attractive...
This paper describes a dual-band clock and data recovery circuit using a new half-rate linear phase detector. With the proposed sampling scheme, the phase detector produces UP/DN signals with equal pulsewidth and thus eliminates the demand of current scaling in the charge pump. The test chip fabricated by CMOS 0.18 ??m 1P6M process can operate at 2.7 and 1.62 Gbps which satisfies the DisplayPort standard...
In this paper, a precise delay generator circuit using the average delay technique is realized in 0.18-mum CMOS 1P6M technology. The proposed delay generator achieves a high resolution and programmable delay by using the average delay technique. Compared with conventional delay generators, the proposed circuit achieves a higher resolution, uses less power, and has a smaller footprint. The input frequency...
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