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In this paper, we propose a low-power VLSI implementation of H.264/AVC baseline decoder. A systematic methodology for power reduction is proposed and applied at various design abstraction levels. At the algorithm level, the computational complexity is optimized. At the architecture level, pipelining and parallelism are widely adopted to reduce the operating frequency; hierarchical memory organization...
In this paper, we propose a low-power H.264/AVC baseline decoder. A systematic methodology for power reduction at all design levels for video decoding is proposed and applied. Power consumption is optimized at algorithm, architecture, circuit, and physical levels. The VLSI implementation results show that with UMC 180 nm technology, the proposed design is able to decode QCIF 30 fps at 1.5 MHz. It...
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