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We report low Vt (Vt,Lg=1μm=±0.26V) high performance CMOS devices with ultra-scaled Tinv down to Tinv~8Å using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme show for the same high-k/metal gate stack (1) 3Å reduction in nMOS and pMOS Tinv (2) 220mV lower long channel...
This paper is the first to provide a comprehensive study on the layout dependence of scaled Si1-xGex-channel pFETs. Drive current enhancement up to 90% is demonstrated for Si0.55Ge0.45-channel pFETs with LG = 35 nm and EOT = 0.9 nm when the transistor width (W) is scaled from 10 μm to 110 nm. This is attributed to a change in channel stress from biaxial compressive at large W to the more beneficial...
We report high yield sub-0.1μm2 SRAM cells using high-k/metal gate FinFET devices. Key features are (1) novel fin patterning strategy, (2) double gate patterning (3) new SRAM cell layout and (4) EUV lithography and robust etch/fill/CMP for contact/metal 1.0.099μm2 FinFET 6T-SRAM cells show good yield. And smaller cells (0.089μm2) are functional. Further yield improvement is possible by junction optimization...
We demonstrate electrically functional 0.099 μm2 6T-SRAM cells using full-field EUV lithography for contact and M1 levels. This enables formation of dense arrays without requiring any OPC/RET, while exhibiting substantial process latitudes & potential lower cost of ownership (single-patterning). Key enablers include: 1) high-k/metal gate FinFETs with Lg˜40 nm, 12-17 nm wide Fins, and cell β ratio...
We report on a major advancement in full-field EUV lithography technology. A single patterning approach for contact level by EUVL (NA=0.25) was used for the fabrication of electrically functional 0.186 mum2 6T-SRAMs, with W-filled contacts. Alignment to other 193 nm immersion litho levels shows very good overlay values les20 nm. Other key features of the process are: 1) use of high-k/Metal Gate FinFETs...
While the potential of FinFETs for large-scale integration (LSI) was demonstrated before on relaxed device dimensions, in this paper we present performance data of aggressively scaled transistors, ring oscillators and SRAM cells. FinFET SRAMs are shown to have excellent VDD scalability (SNM=185 mV at 0.6 V), enabling sub-32 nm low-voltage design.
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