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The most widespread 16-bit multiplier architectures are compared in terms of area occupation, dissipated energy, and EDP (Energy-Delay Product) in view of low-power low-voltage signal processing for digital hearing aids and similar applications. Transistor-level simulations including back-annotated wire parasitics confirm that the propagation of glitches along uneven and re-convergent paths results...
Two DSP algorithms for hearing aids have been integrated on silicon in a 0.18 mum CMOS process. Various level-sensitive two-phase clocking schemes have been evaluated in terms of energy efficiency. Actual measurements have confirmed energy savings of 64% over a recently published clock-gated single-edge-triggered one-phase implementation. Most of these improvements can be attributed to the thinning...
A new constant-coefficient FIR filter architecture is hereby presented, specifically designed for a VLSI adaptive directional microphone for hearing aids. Gate-level simulations targeting a 0.25 mum process point out relevant power savings compared to both the fully time-shared reference design (-80%) and a recently published low-power circuit (-32%), with a limited 11% area overhead compared to the...
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