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In this brief, we presented a bulk-gate controlled circuit for improving a power supply rejection ratio (PSRR) of a low-dropout voltage regulator (LDO), which deteriorated due to lowering of a power consumption. A test chip was fabricated using a 0.18-??m complimentary metal-oxide-semiconductor process, and experimental results demonstrated that the proposed circuit provides the PSRR that improved...
In this work, a Bulk-Gate Controlled Circuit, for improving power supply rejection ratio (PSRR) of a Low Dropout Voltage Regulator (LDO) which deteriorates due to lowering of power consumption is proposed. A test chip was fabricated using 0.18-mum CMOS process. Experimental results of the test chip demonstrate that the proposed circuit provides a high performance of PSRR which is up to 77 dB at 10...
In this work, we propose a design technique of low power fully CMOS low-dropout voltage regulator (LDO) based on quick response (QR) circuit to improve the load transient response. Implemented in 0.18 mum CMOS technology, the LDO with proposed QR circuit can achieve a fast load transient responses with less transient overshoot or undershoot when driving a large load current. For 1 muF decoupling capacitor...
In this paper, a low power current protection circuit implemented in LDOs is presented. The proposed circuit, designed in 0.35 mum CMOS process, provides a precise limiting current as well as holding current with low dependency on both supply voltage and regulator output voltage. The experimental results showed the proposed circuit is operable in the regulator output voltage range VOUT = 1.2 V to...
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