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A low-power content-addressable memory (CAM) using a differential match line (ML) sense amplifier is proposed in this work. The proposed self-disabled sensing technique can choke the charge current fed into the ML right after the matching comparison is generated. Instead of using typical nor/ nand-type CAM cells with the single-ended ML, the proposed novel nand CAM cell with the differential ML design...
A scheme that ATPG-based technique for reducing shift and capture power during scan testing is presented without any influence on fault coverage. This paper presents an X-filling approach called adjacent backtracing fill (AB-fill). After AB-fill approach for at-speed scan testing, all of test patterns have assigned as partially-specified values with a small number of don't care bits (x) as in test...
In this paper, new compression architecture is proposed for multiple scan-chains. We use buffers to hold back data, and use read enable signals to filter useless data. We use only four extra channels and less hardware for largest ISCAS'89 circuits to reduce test data volume and shift-in power. The average of peak/WTC shift-in turns to 3x/6.6x, after comparing (Wang and Chakrabarty, 2008) and our method...
This paper presents a test slice difference (TSD) technique to improve test data compression. It is an efficient method and only needs one scan cell. Consequently, hardware overhead is much lower than cyclical scan chains (CSR). As the complexity of VLSI continues to grow, excessive power supply noise has become seriously. We propose a new compression scheme which smooth down the switching activity...
In recent years, power dissipation is a large challenge for IC design. Furthermore, the capacitance excessive transition may lead to circuit reliable reduction and heat problem. In this paper, we proposed a new algorithm to reduce the transition count of scan cell during capture operation. The clock gating technique, fault diagnosis, and fault dropping are used to decrease the capture power dissipation...
In this paper, we present a low power strategy for test data compression that is called ldquobreak-independent-table (BIT) encodingrdquo. In addition, we present a new decompression scheme for test vectors that is called ldquotest slice difference techniquerdquo to solve huge test data volume that must be stored in the tester memory. About how reducing power dissipation problem, we present an extremely...
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