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Electrostatic discharge (ESD) protection becomes essential to advanced integrated circuits (IC). Very fast IEC-ESD failure and protection design are emerging challenges for contemporary ICs, particularly for consumer and portable electronics. This paper presents a new mixed-mode IEC-ESD simulation-design method, which involves process, device, circuit and system level simulation to accurately address...
This paper discusses general procedures for simulation, design optimization, measurement and modeling of accurate and scalable on-chip RF spiral inductors in standard foundry CMOS for industrial applications. Electro-magnetic (EM) solver is used to simulate and optimize design of a library of inductors with various dimensions and specifications aiming to provide accurate and scalable inductors for...
This paper reviews key factors to practical ESD protection design for RF and analog/mixed-signal (AMS) ICs, including general challenges emerging, ESD-RFIC interactions, RF ESD design optimization and prediction, RF ESD design characterization, ESD-RFIC co-design technique, etc. Practical design examples are discussed. It means to provide a systematic and practical design flow for whole-chip ESD protection...
RF ESD protection circuitry design emerges as a big challenge to RF IC design, where the main problem is associated with performance degradation of RF IC due to ESD-induced parasitics. It has been difficult to incorporate the ESD impacts into RF IC design due to lack of proper co-design approach and ESD device models. This paper presents a new ESD-RFIC co-design methodology, including RF ESD design...
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