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A novel VLSI architecture for digital multimedia post-processing system is presented. First, the sequence of the post-processing de-blocking filter is modified, and the filter algorithm is optimized. Second, the frames are extended at the upper and left frame boundaries for 8 pixels in depth in order to avoid the irregularity and simplify the control unit. At last a macro block-based together with...
Now a number of architectures of intra frame decoder for H. 264 have been put forword, but most of them use an original decoding order. That is current block's prediction shouldn't be executed until previous block's reconstruction is finished. Obviously, this introduces much redundant time. In this paper, we proposed a 4 times 4 pipelined architecture in which current block's prediction can be paralleled...
A new architecture based on parallel FIR systolic arrays for motion compensation interpolation in H.264/AVC is presented in this paper. Unlike other interpolation architectures based on traditional adder tree or one systolic FIR, this design has advantages of both the pipeline property of systolic FIR filter and high parallel property. It has following characteristics: First, it uses several strategies...
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