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Exascale computing represents the next leap in the HPC race. Reaching this level of performance is subject to several engineering challenges such as energy consumption, equipment-cooling, reliability and massive parallelism. Model-based optimization is an essential tool in the design process and control of energy efficient, reliable and thermally constrained systems. However, in the Exascale domain,...
Long lifetime is the most pursued goal in Wireless Sensor Networks (WSNs). As communication is typically the most energy consuming task, a lot of effort has been devoted to design energy efficient communication protocols using duty-cycling in the last decades. However, in the recent years, a new kind of Ultra Low Power (ULP) receivers, called Wake-up Receivers (WuRx), is emerging. These devices allow...
On-chip L2 cache architectures, well established in high-performance parallel computing systems, are now becoming a performance-critical component also for multi/many-core architectures targeted at lower-power, embedded applications. The very stringent requirements on power and cost of these systems result in one of the key challenges in many-core designs, mandating the deployment of highly efficient...
Wireless Body Area Networks (WBAN) present a variety of Power Management challenges ranging from radio protocols, to node components. In this work we focus on optimal exploitation of low power operating points in micro-controller-based sensor nodes under sensor sampling frequency constraints. We introduce general techniques to link the selection of optimal operating points, and operating point transitions,...
Wireless Body Area Networks (WBANs) can take advantage of many wireless protocols. Among them, Bluetooth is a good candidate since its widespread adoption guarantees compatibility with a number of devices and significantly reduces development time. In most cases data collected from different sensors on different nodes need to be synchronized. We present a synchronization protocol that makes use of...
Barrier synchronization is a key programming primitive for shared memory embedded MPSoCs. As the core count increases, software implementations cannot provide the needed performance and scalability, thus making hardware acceleration critical. In this paper we describe an interconnect extension implemented with standard cells and with a mainstream industrial toolflow. We show that the area overhead...
In video surveillance there is an ever-growing demand for heavily distributed radio cooperating objects that Wireless Sensor Networks (WSNs) can satisfy. We present a preliminary study of an energy efficient multimodal WVSN using a main node deciding which camera to trigger based on the information from a Pyroelectric InfraRed (PIR) network. The evaluation of the proposed approach against the solution...
Historically, processor performance has increased at a much faster rate than that of main memory and up-coming NoC-based many-core architectures are further tightening the memory bottleneck. 3D integration based on TSV technology may provide a solution, as it enables stacking of multiple memory layers, with orders-of-magnitude increase in memory interface bandwidth, speed and energy efficiency. To...
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