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A phase-locked loop (PLL) that can be used in a zero-IF radio architecture with beamforming for AV-OFDM with 16-QAM modulation is demonstrated for the first time in 40 nm LP CMOS technology. This type II integer-N PLL of order four includes an injection-locked divide-by-4 prescaler and two quadrature series-coupled VCOs, operating in 63-70 GHz and 72-81 GHz frequency bands. It achieves -85 dBc/Hz...
A Software-Defined Radio (SDR) analog front-end is presented that provides extensive programmability of LO generator, LNA, mixers, baseband filters and PPA, supporting various wireless communication standards while guaranteeing a near-optimal power/performance trade-off at any time. The circuit is integrated in a 0.13 mum CMOS technology with 1.2 V supply voltage. This transceiver covers the frequency...
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