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A third-order multi-channel incremental ADC with a 5-level quantizer is presented. An optimal decimation filter is used which minimizes the weighted sum of the thermal and quantization output noises. Digital correction is used to suppress mismatches in the multi-bit DAC. The prototype obtained a signal-to-noise-and-distortion ratio of 81.5 dB, within a total of 21.7 kHz signal bandwidth at a 10 MHz...
A dual-path 2-0 cascaded delta-sigma (MASH) ADC was implemented with fast digital correction of both DAC errors and MASH mismatch errors. The digital correction techniques greatly reduced the requirements on the analog circuits. The dual-path structure allows fast convergence and improved accuracy for the correction. Using a 20 MHz clock, the prototype chip achieved an 84 dB dynamic range in a 1.25 MHz...
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