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This paper demonstrates, for the first time, a high density, low cost redistribution layer (RDL) stack-up using a novel, ultra-thin dry film photosensitive dielectric material for panel scale 2.5D glass interposers and fan-out packages. The salient features of this semi-additive process based RDL demonstrator include: (1) A two metal layer RDL structure with integration of 5 µm microvias at 20 µm...
Silicon interposers with through-silicon vias (TSVs) have been developed in single-crystalline silicon wafer to address the high I/O density requirements between high performance logic, memory, graphic, and other devices. However, single-crystalline silicon interposers suffer from many shortcomings such as high cost, low electrical performance, and reliability. To overcome these shortcomings of traditional...
This paper presents the first demonstration of polycrystalline silicon interposers with fine pitch through package vias (TPV), with less than 5μm RDL lithography at 50μm pitch copper microbump assembly. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high...
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