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An optimized SCR structure was proposed for high turn-on speed and low parasitic capacitance in FinFET CMOS process. Experimental results indicate that the proposed SCR structure delivers the best known results among the literatures (140mA/fF). By adopting the structure, ESD protection design for multi Gb/s transceiver can be simply realized.
Double-patterning lithography is required at 20 nm node for planar CMOS. At the 16 / 14 nm node, in order to deliver attractive amount of Performance-Power-Area enhancement, 3-D FinFETs are required. Close collaboration at design ecosystem among fabrication foundry, EDA vendors, IP vendors, packaging vendors, and design houses is crucial for successful migration to FinFET circuits. This paper describes...
A new gate driven 3.3V ESD clamp circuit using 1.8V transistor is proposed. This new clamp circuit is suitable for ESD protection of legacy 3.3V I/O interface circuit in SOC chips which use only 1.8V I/O transistors. This clamp along with 3.3V I/O have been demonstrated in 40nm 1.8V process. Life-time test can pass 1000-hours prolonged operation. ESD/Latch-up can pass HBM 3KV, MM 300V, and +/-200mA...
Silicon nanowire transistor with side-gate and back-gate has been fabricated by electron beam lithography combined with dry oxidation on a doped silicon-on-insulator wafer. The effects of back-gate and side-gate on the properties of single electron transport were investigated by measuring the channel current as function of the applied gate voltages. The tunable single electron effect and Coulomb oscillations...
Capacitance-voltage (C-V) and frequency dependent conductance-voltage (G-V) measurements have been carried out to investigate the charging and discharging effect induced by interface states and nanocrystalline Si (nc-Si) in floating gate MOS structures. Distinct conductance peaks are observed in the G-V curves for the floating gate with and without nc-Si dots. Based on the calculation of interface...
The nc-Si nonvolatile memory devices with high performance have been fabricated by using general CMOS techniques. High resolution transmission electronic microscope (HRTEM) shows that the average size of nc-Si is 8 nm and its density is 3×1011/cm2. The performance of programming/ erasing and retention time is mainly depending on the quality and thickness of tunnel layer and control layer. The results...
Multi-Harmonic Phase Analysis (MHPA) has been developed to quantify left-ventricular (LV) mechanical dyssynchrony with gated single photon emission tomography (SPECT) myocardial perfusion imaging (MPI). Although MHPA has shown promising clinical results, it needs to be optimized technically. The purpose of this study is to develop a tool to simulate LV mechanical dyssynchrony in gated SPECT MPI using...
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