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We have fabricated and successfully tested an analog vector-by-matrix multiplier, based on redesigned 10×12 arrays of 55 nm commercial NOR flash memory cells. The modified arrays enable high-precision individual analog tuning of each cell, with sub-1% accuracy, while keeping the highly optimized cells, with their long-term state retention, intact. The array has an area of 0.33 μm2 per cell, and is...
Resistive switching memories have been identified as an enabling technology for a variety of emerging computing applications, including neuromorphic and logic-in-memory computing. For example, analog tuning of the memory state combined with high integration density of memristors is needed for very compact implementation of synapses, the most numerous devices in artificial neural networks and would...
High-precision individual cell tuning was experimentally demonstrated, for the first time, in analog integrated circuits redesigned from a commercial NOR flash memory. The tuning is fully automatic, and relies on a write-verify algorithm, with the optimal amplitude of each write pulse determined from runtime measurements, using a compact model of cell's dynamics, fitted to experimental results. The...
This is a brief review of our recent work on memristor-based spiking neuromorphic networks. We first describe the recent experimental demonstration of several most biology-plausible spike-time-dependent plasticity (STDP) windows in integrated metal-oxide memristors and, for the first time, the observed self-adaptive STDP, which may be crucial for spiking neural network applications. We then discuss...
Neuromorphic pattern classifiers were implemented, for the first time, using transistor-free integrated crossbar circuits with bilayer metal-oxide memristors. 10×6- and 10×8-crosspoint neuromorphic networks were trained in-situ using a Manhattan-Rule algorithm to separate a set of 3∗3 binary images: into 3 classes using the batch-mode training, and into 4 classes using the stochastic-mode training,...
We have modified a commercial NOR flash memory array to enable high-precision tuning of individual floating-gate cells for analog computing applications. The modified array area per cell in a 180 nm process is about 1.5 μm2. While this area is approximately twice the original cell size, it is still at least an order of magnitude smaller than in state-of-the-art analog circuit implementations. The...
It has been known that, real right half plane (RHP) zeros imply serious limitations on the performance of nonminimum phase systems. Feedback cannot remove these limitations, mainly because RHP zeros cannot be cancelled by unstable poles of the controller since such a cancellation leads to internal instability. Hence, the idea of using fractional order systems in partial cancellation of the RHP zeros...
This paper deals with the boundary control problem for a certain class of linear infinite-dimensional systems commonly known as fractional-delay systems. It is assumed that the systems under consideration are, in general, described by multi-valued transfer functions. In this paper, we restrict our studies to a class of multi-valued transfer functions which are defined on a Riemann surface with limited...
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