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We propose a 256×8-bit ultra-low power asynchronous memory design with emphases on micropower, improved soft errors, and operation robustness (i.e. innately self-timed operation which can tolerate Process, Temperature, and Voltage variations) for sub-threshold operation (i.e. the supply voltage VDD is below the threshold voltage of transistors). The proposed memory, to the best of our knowledge, is...
In this paper, we propose a methodology to de- synchronize a synchronous digital-logic system to obtain a system based-on asynchronous logic with equivalent input/output (I/O) functionality. The motivation is to compare the performance of synchronous and asynchronous implementations, especially on power dissipation and process variation robustness. To de- synchronize the controller, several transformations...
Two 128-point 16-bit radix-2 FFT/IFFT processors based on synchronous-logic (sync) and asynchronous-logic (async) for low voltage (1.1-1.4 V) energy-critical low-speed hearing aids are described. The two processors herein are designed with the same function and similar architecture, and the emphasis is energy efficacy. The async approach, on average, features ~37% lower energy per FFT/IFFT computation...
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