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This paper presents a reconfigurable SC audio ΣΔ modulator implemented in a 0.18-mm CMOS technology. The 0.4-mm2 ΣΔ modulator, based on a 2-2 MASH architecture, features several different operating modes in which noise-shaping order, number of output bits, sampling rate, and signal bandwidth can be programmed. The power consumption is always minimized for the selected operating mode. The achieved...
A low-power front-end for a capacitive MEMS accelerometer sensor is presented. The read-out front-end includes the analog preamplifier (to sense the signal coming from the MEMS) and a Successive-Approximation A/D Converter. The off-chip MEMS is a capacitive accelerometer. Constant-charge Capacitance-to-Voltage conversion has been used with a programmable-gain (to accommodate different MEMS sensor...
In this work a high-resolution, low power, successive approximation register (SAR) ADC for X and Gamma Ray Silicon Drift Detector read-out in space applications is presented. The proposed scheme, implemented at transistor level in 0.35 μm CMOS technology consists in an input buffer, a high resolution comparator, a logic control circuit and a capacitive DAC. Simulations carried out in worst case matching...
In this paper we present a 10-bit, two-bit per cycles successive-approximation A/D converter (ADC). The circuit, operated at 60 MHz clock frequency, achieves a sampling frequency of 10 MHz, requiring only 6 clock cycles to accomplish a conversion. The ADC exploits three comparators to resolve two bits during each conversion cycle. To avoid the severe performance degradation due to offset mismatches...
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