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FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (Vt) necessary for multiple Vt solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain current (Ion) variability (0.37 %µm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability...
The functional tri-gate flash memories with splitgate have been demonstrated for the first time, and its Vt variabilities before and after one P/E cycle have be systimetically compared with stack-gate ones. It was confirmed that split-gate shows smaller Vt distribution after erase and excellent over-erase immunity compared to those of stack-gate. Moreover, it was found that BVDS is higher than 3.2...
We experimentally investigated the device performance of n+- poly-Si/PVD-TiN stacked gate FinFETs with different Hfin's. It was found that mobility enhances in the tall Hfin devices due to the increased tensile stress. However, as Lg decreases, Ion for tall Hfin case becomes worse probably due to high Rsp. It was also confirmed that Vth variation increases with increasing Hfin due to the rough etcing...
The threshold voltage (Vt) in scaled poly-Si channel FinFETs and tri-gate flash memories with poly-Si floating gate (FG) was systematically compared with crystal channel ones, for the first time. It was found that some superior Id-Vg characteristics are observed in the scaled poly-Si channel FinFETs with gate length (Lg) down to 54 nm or less. The standard deviation of Vt (σVt) of poly-Si channel...
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