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Well designed tunneling green transistor may enable future VLSIs operating at 0.1V. Sub-60mV/decade characteristics have been convincingly demonstrated on 8" wafers. Large ION at low VDD are possible according to TCAD simulations but awaits verification. VDD scaling will greatly benefit from low (effective) band gap energy, which may be provided by type II heterojunctions of Si/Ge or compound...
Si-tunneling field effect transistors (TFETs) with a record Ion >100 μA/μm and high Ion/Ioff ratio (> 105) at Vds=1V are reported. Using an optimal spike and millisec flash anneal coupled with an engineered source-gate overlap through a gate-last process, Si TFETs have been demonstrated with 10 to 1000 times greater current than previously reported. The devices exhibit negative differential...
We report a novel tunneling field effect transistor (TFET) fabricated with a high-k/metal gate stack and using nickel silicide to create a special field-enhancing geometry and a high dopant density by dopant segregation. It produces steep subthreshold swing (SS) of 46 mV/dec and high ION/IOFF ratio (~108) and the experiment was successfully repeated after two months. Its superior operation is explained...
A new tunneling transistor structure is introduced that offers several advantages over prior designs. Notably, tunneling area is substantially increased. Turn on/off swing is improved by engineering doping profile to ensure tunneling initiates in high electric field region. TCAD simulations explore the critical design considerations. The concept of heterojunction tunneling is introduced as a means...
Tunnel field effect transistors (TFETs) with record high ION/IOFF ratio (>106) for low-voltage (0.5 V) operation are achieved by using germanium in the source region to achieve a small tunnel bandgap. The measured data are well explained by the theoretical band-to-band tunneling current model. Using the calibrated analytical model, the energy-delay performance of TFET-based technology is compared...
A novel hetero-tunnel transistor (HtFET) with a heterostructure and ultra shallow junction parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling Vdd down to 0.2 V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.
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