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We demonstrate multi-VT engineering on both CMOS bulk and FinFET devices through As implantation into a 1.0nm EOT TiN/high-K gate stack within a single metal single dielectric approach. We determine a As implantation process window enabling VT tuning without any device degradation. It is shown that this approach is suitable for multi-VT engineering with aggressively scaled dielectrics and, particularly,...
Two SMSD gate first planar CMOS devices were demonstrated. Vtn/Vtp= +0.49V/-0.48V were achieved by adjusting TiN to p-like metal and As I/I on nMOS. This enables the equivalent +/-0.2V low Vt target of N22 fully depleted CMOS technologies. Vtn/Vtp= 0.52/-0.55 were obtained by transforming PVD-TiN/Ti into n-like metal TiN/TiSix for nMOS and by Al I/I on TiN/Ti for pMOS. Al diffusion was facilitated...
In this paper we describe a novel fully self-aligned HBT architecture, which enables a maximum reduction of device parasitics. TCAD simulations show that this architecture is capable of achieving fT/fmax values of 295/425 GHz for an effective emitter area of 0.13times5 mum2. In this new process approach, which is fully CMOS compatible, the collector and base are grown in a single-step non-selective...
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