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We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 0.13 mum CMOS process on 200 mm wafers. The top die is thinned down to 25 mum and bonded to the landing wafer by Cu-Cu thermo-compression. Both top and landing wafers contain CMOS finished...
The influence of thinning standard 130-nm CMOS technology device wafers to residual silicon thicknesses of 20 and 5 mum has been studied. Electrical performance was evaluated at wafer level by characterizing various basic device parameters before and after thinning. An increase in the well sheet resistance and a reduction in the gate leakage current were observed. However, both at 25degC and 100degC,...
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