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Conventional Von Neumann microprocessors are inefficient for supporting machine intelligence due to layers of abstraction, limiting the feasibility of machine-learning frameworks in critical applications. A new approach for architecting intelligent systems, using physical equivalence and leveraging emerging nanotechnology, can pave the way to machine intelligence everywhere.
Probabilistic graphical models are powerful mathematical formalisms for machine learning and reasoning under uncertainty that are widely used for cognitive computing. However, they cannot be employed efficiently for large problems (with variables in the order of 100K or larger) on conventional systems, due to inefficiencies resulting from layers of abstraction and separation of logic and memory in...
We present a novel multi-valued computation framework called Wave Interference Functions (WIF), based on emerging non-equilibrium wave phenomenon such as spin waves. WIF offers new features for data representation and computation, which can be game changing for post-CMOS integrated circuits (ICs). Information encoding wave attributes inherently leads to multi-dimensional multi-valued data representation...
Maintaining power scaling trend and cell stability are critical challenges facing CMOS SRAM at sub-20nm technologies. These challenges primarily stem from the fundamental limitations of MOSFETs, and the rigid device doping and sizing requirements of underlying SRAM design. In this paper, we propose a new volatile memory architecture called Tunnel FET based Random Access Memory (TNRAM) that solves...
Spin Wave Functions (SPWFs) realize computation with spin waves, offering several benefits and new features over CMOS. SPWF technology potentially opens up new directions for designing microprocessors with increased capabilities over current implementations. Towards this end, as a preliminary work an 8-bit embedded processor is explored here using SPWFs and evaluated in terms of its power, area and...
A nanowire-based field-programmable computing platform is presented featuring intrinsic fine-grained device-level reconfiguration without emulation (i.e. no look-up tables involved) using programmable cross-nanowire transistors, and regular physical implementation with relaxed manufacturing requirements at nanoscale. This approach can potentially provide orders of magnitude benefits in terms of area,...
Nanoscale 3D-integrated Application Specific ICs (N3ASICs) [1], a computing fabric based on semiconductor nanowire grids, is targeted as a scalable alternative to end-of-the-line CMOS. In contrast to device-centric approaches like CMOS, N3ASIC design choices across device, circuit and architecture levels are geared towards reducing manufacturing requirements while focusing on overall benefits. In...
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