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The Carbon Nano Tube Field Effect Transistor (CNTFET) is a promising device to supersede the MOSFET at the end of the technology roadmap of CMOS. When a CNTFET is fabricated, only some of the CNTs could be deposited. As reported in an earlier paper, this significantly degrades the performance of the CNTFET. In this paper, the delay analysis of a CNTFET in the presence of undeposited CNTs (as defects)...
Asynchronous design is a promising alternative for emerging technologies facing extreme parameter variation, severe timing/clock skew and power consumption issues. However, the complexity in design and test is one of the major obstacles for the widespread use of asynchronous circuits in digital design. Circuits utilizing templates are often implemented to mitigate the design complexity of an asynchronous...
Addition is a significant operation in soft computing, several sequential adder designs have been proposed in the technical literature. These adders show different operational profiles, some of them are inspired by biological networks or the probabilistic nature of nanometric devices (such as the Lower-part OR Adder (LOA) and the Probabilistic Full Adder (PFA)). This paper deals with the reliability...
This paper presents a detailed characterization of the effects of intra-gate resistive open defects on nanoscaled CMOS gates as causing faults with timing and pattern sequence dependency. The values of the least detectable resistance are established for different feature sizes using HSPICE. It is found that as the feature size is reduced, the value of the least detectable resistance increases in the...
The occurrence of a multiple node upset is likely to increase significantly in nanoscale CMOS due to reduced device size and power supply voltage scaling. This paper presents a comprehensive treatment (model, analysis and design) for hardening a memory cell against a soft error resulting in a multiple node upset at 32nm feature size in CMOS. A novel 13T memory cell configuration is proposed, analyzed,...
This paper presents a novel memory cell consisting of a memristor and ambipolar transistors. Macroscopic models are utilized to characterize the operations of this memory cell. A detailed treatment of the two basic memory operations (write and read) with respect to memristor features is provided; particular, emphasis is devoted to the threshold characterization of the memristance and the on/off states...
This paper presents a novel memory cell consisting of a memristor and ambipolar transistors. Macroscopic models are utilized to characterize the operations of this memory cell. A detailed treatment of the two basic memory operations (write and read) with respect to memristor features is provided; particular, emphasis is devoted to the threshold characterization of the memristance and the on/off states...
The Carbon NanoTube Field Effect Transistor (CNTFET) is a promising device to supersede the MOSFET at the end of the technology roadmap of CMOS. One of the likely defect types that may occur in the manufacturing process is that the diameter of a CNT could be changed and not all CNTs are deposited. This paper deals with the degradation scenario in which different CNT parameters (the diameter, the number,...
Quantum-dot Cellular Automata (QCA) is one of the emerging technologies that have been advocated to overcome the physical limitations of CMOS in the nano ranges. For QCA to be a viable alternative to CMOS in the decades ahead, tools and methodologies at physical and logic levels are urgently needed in support of all design phases. This paper presents an HDL based framework and related models to simulate...
This paper presents the characterization and design of a Static Random Access Memory (SRAM) cell at nano scale ranges. The proposed SRAM cell incorporates a Single-Electron (SE) turnstile and a Single-Electron Transistor (SET)/MOS circuit in its operation, hence its hybrid nature. Differently from previous cells, the hybrid circuit is utilized to sense (measure) on a voltage-basis the presence of...
Open defects are extremely common in CMOS circuits. They can either be a partial or complete breaking of an input line. The complete breaking of the line is referred to as strong or full open defect. Until few years ago, a full open defect on any interconnecting line has been considered as floating. In nanometric CMOS technology, in which gate leakage currents are not negligible, full open defect...
Large and complex structures commonly referred to as patterns can be generated using DNA-like self-assembly. Self-assembly has an algorithmic nature, that is suitable for diverse applications in nano computing and manufacturing. This paper deals with the error characterization and modeling encountered when only a partial pattern is grown by DNA self-assembly. Partial growth is accomplished by clipping...
The Carbon NanoTube Field Effect Transistor (CNTFET) is a promising device to supersede the MOSFET at the end of the technology roadmap of CMOS. When designing and manufacturing a CNTFET, additional features such as pitch, number and position of the CNTs must be considered to assess its performance. One of the defect types that can occur when fabricating a CNTFET, is the absence of some CNTs following...
This paper presents an extensive analysis of the degradation of solar cells due to time and temperature. This analysis is based on the single diode model (SDM) and relies on HSPICE to initially establish through simulation the relationships between model parameters, efficiency and process variations. The analysis is extended to the operational temperature and time by extracting the degradation in...
This paper presents a detailed analysis of an architectural pipeline scheme for Quantum-dot Cellular Automata (QCA); this scheme utilizes the so-called Bennett clocking for attaining high throughput and low power dissipation. In this arrangement, computation stages (utilizing Bennett clocking) and memory stages combine the low power dissipation of reversible computing with the high throughput feature...
This paper presents a novel approach for compressing functional test data in automatic test equipment (ATE). A practical technique is presented for 2 dimensional (2D) reordering of test data in which additionally to test vector reordering, column reordering is also applied. An ATE based approach to extract the original test vectors from the 2D ordered data is presented. The advantage of the approach...
This paper proposes the control of monomer concentration as a novel improvement of the kinetic tile assembly model (kTAM) to reduce the error rate in DNA self-assembly. Tolerance to errors in this process is very important for manufacturing highly dense ICs; the proposed technique significantly decreases error rates (i.e. it increases error tolerance) by controlling the concentration of monomers....
This paper presents a novel method that utilizes multi-site and multi-probe facilities in an ATE for substrate testing. The test time for a batch can be considerably reduced by efficiently utilizing an ATE with a number of flying-probes and multiple substrates under test (SUTs). An analytical model that predicts very accurately the batch test time is proposed. This model establishes the optimal multi-site...
This paper presents two load board designs for hierarchical calibration of largely populated ATE. Compound dot technique and phase detector are used on both boards to provide automatic and low cost calibration of ATE with or without a single reference clock. Two different relay tree structures are implemented on the two boards with advanced board design techniques for group offset calibration. Various...
Recent developments for biosensors have been mainly focused on miniaturization and exploratory use of new materials. It should be emphasized that the absence of a novel "in-situ self-calibration/diagnosis technique" that is not connected to an external apparatus is a key obstacle to the realization of a biosensor for continuous use with minimum attendance. To address this deficiency, a novel...
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