The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A Look-Up Table (LUT) shows modest performance (delay and power) when used as a universal logic module (ULM) for implementing all possible combinational functions; moreover, the complete programmability of a LUT (so for all functions) incurs in a significant circuit complexity. Few approaches have been proposed by which a LUT is replaced by circuits; this is possible because in practice, the number...
This paper presents the designs of two digital circuits in which processing of data (stored in volatile and non-volatile memories) is locally performed and routed; these circuits are referred to as data-centric and therefore, amenable to Near-Memory (NM)operation. Two circuits are proposed; they utilize at logic level a 2-2AOI gate, but with different types of selector. Simulation results using HSPICE...
This paper deals with the integration of several emerging technologies (embedded DRAM (eDRAM) and Phase Change Memory (PCM)) with SRAM to leverage their operational features and achieve a hybrid L2 cache for improvements in density and power consumption. A novel hybrid cache replacement and migration policy is proposed; a hybrid macrocell is also designed using a different number of eDRAM, PCM and...
The increasing amount of circuit density possible in CMOS technology has the consequence of also increasing the power consumption of circuits using the technology. One possible method of offsetting these increased power demands is to use approximate computing designs in circuits where complete accuracy is not a strict requirement. These circuits use fewer logic gates which reduces power consumption...
A Physical Unclonable Function (PUF) is often used to uniquely identify an integrated circuit by extracting its internal random differences using so-called Challenge Response Pairs (CRPs). As CRPs include unique information about the underlying hardware variations, PUF design is a promising approach to provide authentication and IP-protection capabilities. In this paper, an XOR-gate-based configurable...
A multiplier has a significant impact on the speed and power dissipation of an arithmetic processor. Precise results are not always required in many algorithms, such as those for classification and recognition in data processing. Moreover, many errors do not make an obvious difference in applications such as image processing due to the perceptual limitations of human beings. Error-tolerant algorithms...
Approximate or inexact computing is an attractive design methodology for low power design and is achieved by relaxing the requirement of accuracy. This paper proposes the first approximate design of Redundant Binary (RB) multipliers. An approximate Booth encoder and an approximate RB compressor are proposed and analyzed. RB multipliers are proposed based on the proposed approximate Booth encoder and...
This paper proposes a new approximate scheme for a coordinate rotation digital computer (CORDIC) design; this scheme is based on modifying the existing Para-CORDIC architecture with multiple approximations. These approximations make possible a relaxation of the CORDIC algorithm itself, such that a fully parallel approximate CORDIC (FPAX-CORDIC) scheme is designed. This scheme avoids the memory register...
This paper proposes a two-dimensional (2D) convolver in which both approximate circuit- and algorithm-level techniques are utilized in the design. Truncation is used as circuit techniques, while bit-width reduction is utilized at the algorithm level. These different techniques are related to the configuration of the convolver by which its operation can be configured to meet different and often contrasting...
This paper presents two circuits for implementing the restore operation of a non-volatile (NV) memory cell in which data from a programmable metallization cell (PMC) can be copied (restored) into a static random access memory (SRAM). In the first proposed design, a transmission gate is added to each row of cells of the memory array in which a concurrent error detection (CED) circuit is also present...
This paper proposes a design of a Ternary Content Addressable Memory (TCAM) cell using racetrack memories (RMs) for non-volatile operation. Four RMs are utilized as storage elements and CMOS transistors are used as control elements for executing the write and search operations. The search operation of the TCAM cell utilizes novel circuits to read the RMs and compare data at cell and array levels....
Approximate/inexact computing has become an attractive approach for designing high performance and low power arithmetic circuits. Floating-point (FP) arithmetic is required in many applications, such as digital signal processing and machine learning. Different approximate FP multipliers are proposed in this paper, the accuracy and the circuit requirements of these designs are assessed to select the...
A parallel decimal multiplier is proposed in this paper to improve performance by mainly exploiting the properties of three different binary coded decimal (BCD) codes, namely the redundant BCD excess-3 code (XS-3), the overloaded decimal digit set (ODDS) code and BCD-4221/5211 code, hence this design is referred to as hybrid. The signed-digit radix-10 recoding with the digit set {-5, 5} and the redundant...
This paper proposes the design of an adaptive filterin stochastic circuits. The proposed circuit requires lower areaand power than a conventional stochastic implementation. In theproposed design, the stochastic multiplier is implemented by anXNOR gate, as in a conventional scheme. However, the stochasticadder based on a multiplexer is not a very efficient implementationdue to the three required stochastic...
Approximate or inexact computing has recently attracted considerable attention due to its potential advantages with respect to high performance and low power consumption. This paper presents the design of an approximate multiplier; this approximate multiplier consists of an approximate Booth encoder, an approximate 4-2 compressor and an approximate tree structure. The approximate design is implemented...
The physical unclonable function (PUF) produces die-unique responses and is regarded as an emerging security primitive that can be used for authentication of devices. The complexity of a conventional PUF design based on a ring oscillator (RO) is rather high, so limiting its use in many applications. The configurable ring oscillator (CRO) PUF has been advocated as a possible solution to this issue...
This paper proposes three designs of an inexact adder cell for approximate computing. These cells require a substantially smaller number of transistors compared to an exact full adder cell as well as known inexact designs. These inexact cells are simulated at 45 nm and compared with respect to circuit based metrics (such as energy consumption, delay, complexity and energy delay product) as well as...
We consider technology mapping from factored form (binary leaf-DAG) to lookup tables (LUTs), such as those found in field programmable gate arrays. Polynomial time algorithms exist for (in the worst case) optimal mapping of a single-output function. The worst case occurs when the leaf-DAG is a tree. Previous results gave a tight upper bound on the number of LUTs required for LUTs with up to 5 inputs...
A hybrid memory cell usually consists of a Static Random Access Memory (SRAM) and an embedded Dynamic Random Access Memory (eDRAM) cell; hybrid cells are particularly suitable for cache design. A novel hybrid cache memory scheme (that has also non-volatile elements) is initially proposed; this scheme is assessed through extensive simulation to show significant improvements in performance. Different...
This paper presents the design of a non-volatile register file using cells made of a SRAM and a Programmable Metallization Cell (PMC). The proposed cell is a symmetric 8T2P (8-transistors, 2PMC) design; it utilizes three control lines to ensure the correctness in its operations (i.e. Write, Read, Store and Restore). Simulation results using HSPICE are provided for the cell as well as the register...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.