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This paper proposes a heterogeneous system platform to speed up the implementation and verification of innovative design for integrating microphone array application. Comparing to state-of-the-art prototyping systems, the proposed platform named MorPACK (morphing package) achieves modularity and flexibility by adopting three concepts: substrate-level modularization, three-dimensional (3D) module stack,...
The present SoC prototyping platforms in the market are usually with stationary connecting architecture, including designated bus protocols and peripheral interfaces. Due to the lack of architectural flexibility, users are not allowed to adapt the architecture for specific applications by on-chip-buses and on-chip-networks. In addition, the system architecture under the FPGA-based SoC may differ from...
This paper presents an efficient memory controller VLSI design for integrating a 3D heterogeneous MorPACK system. The MorPACK system is a platform-based integration system and its structure is stacked by heterogeneous sub-modules. In order to reduce fabrication cost and increase the flexibility of memory extension, a novel multimode memory controller is proposed in this paper. The multimode memory...
Education of embedded systems is essential for Computer Science and Electrical Engineering students. However, traditional courses of embedded systems in the university cannot satisfy all industrial requirements anymore due to the extreme wide applicable area of embedded systems nowadays. In this article, we propose a series of short courses for learning embedded systems. Three hardware platforms focusing...
This paper presents a thermal analysis result for a 3D heterogeneous embedded system integration MorPACK (morphing package) platform. The MorPACK platform is stacked by heterogeneous submodules composed of bare dies, a substrate, connection bridges, and solder balls. Since the tiny, heterogeneous and integrable characteristics of MorPACK platform, it needs to be fabricated in high-density and laminar...
This paper presents a configurable CONCORD platform for Multi-Project System-on-a-Chip (MP-SoC) implementation. The multi-projects platform was created for integrating heterogeneous SoC projects into a single chip. The total silicon prototyping cost for these projects can be greatly reduced by sharing the common SoC platform. A configurable SoC prototyping platform CONCORD is created as a verification...
This paper presents a programmable system-on-chip (SoC) design methodology which integrates multiple heterogeneous SoC design projects into a single chip such that the total silicon prototyping cost for these projects can be greatly reduced by sharing a common SoC platform. In this implementation, an integrated SoC platform is comprised of eight SoC projects. When these eight SoC projects are designed...
With the ever increasing complexity of System-on-a-chip (SoC) and the pressures of short time-to-market and low cost requirements, the platform-based design paradigms have been commonly used for SoC designs. Modular and flexible design becomes very important features for enhancing expandability and re-configurability of the system. The embedded system focuses on specific application instead of general...
This paper proposes a packet-based verification platform with serial link interface for emulating the hardware of the heterogeneous IPs before tape out. With the serial link interface Serializer/Deserializer (SerDes) added between IPs, significant amount of pin counts can be reduced in the platform. An adapter is inserted between IP and SerDes to convert parallel bus into packets and handle the handshaking...
A silicon prototyping methodology is presented for Multi-Project System-on-a-Chip (MP-SoC) implementation. A multi-projects platform was created for integrating heterogeneous SoC projects into a single chip. The total silicon prototyping cost of these projects can be greatly reduced by sharing a common platform. To demonstrate the effectiveness of the proposed methodology, a MP-SoC chip was implemented...
This paper presents a Programmable SoC (Systemon-chip) design methodology which integrates multiple heterogeneous SoC design projects into a single chip such that the total silicon prototyping cost for these projects can be greatly reduced by sharing the common SoC platform. Results show that an integrated SoC platform is comprised of eight SoC projects. When these eight SoC projects are designed...
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