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This paper discusses the design of a setup for short-circuit (SC) testing of 10 kV 10A 4H-SiC MOSFETs. The setup can achieve voltages up to 10 kV and currents in excess of 100A. The main objective during the design was to obtain low parasitic inductance throughout the setup, while at the same time, reduce the complexity and size of the setup by avoiding series connection of DC-link capacitor and by...
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