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As the era of big data approaches, conventional digital computers face increasing difficulties in performance and power efficiency due to their von Neumann architecture. As a result, there is recently a tremendous upsurge of investigations on brain‐inspired neuromorphic hardware with high parallelism and improved efficiency. Memristors are considered as promising building blocks for the realization...
Two hybrid memristor-MOS exclusive OR (XOR) and exclusive NOR (XNOR) logic gates based on Memristor Ratioed Logic (MRL) are presented. The proposed gates present logic states with voltages, and implement the logic operation within one clock cycle. The designs ease the voltage degradation problem of the original MRL logic gates, while consuming fewer area overhead and less delay than their counterparts.
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