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This investigation is based on a traditional AB2 systolic array multiplier to derive a new CED AB2 multiplier using linear block codes. A novel linear encoding algebra is derived to realize parity-check functionality. It is based on the syndrome value, and is adopted to detect errors in the multiplication. Altera FPGA with stratix families to simulate our proposed CED multiplier. In the field GF (2...
This work presents a novel bit-parallel systolic multiplier for the shifted dual basis of GF(2m). The shifted dual basis multiplication for all trinomials can be represented as the sum of two Hankel matrix-vector multiplications. The proposed multiplier architecture comprises one Hankel multiplier and one (2m-1)-bit adder. The algebraic encoding scheme based on linear cyclic codes is adopted to implement...
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