The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A 16 Gb/s 1-tap Infinite impulse response (IIR) + 1-tap discrete-time (DT) decision feedback equalizer (DFE) with integrated clock recovery and adaptation is demonstrated in 28 nm FD-SOI CMOS. Using a CMOS phase rotator, 0.7 unit interval (UI) high-frequency jitter tolerance is achieved when operating mesochronously, and over 0.4 UI operating plesiochronously. The half-rate architecture includes a...
I/O receivers routinely equalize ISI over 10 or more post-cursor UI. IIR DFEs are a low-power technique for canceling long post-cursor ISI tails, and have been demonstrated compensating over 20dB loss at fbit/2 up to 10Gb/s [1–5]. Equalizer adaptation is required to maintain signal integrity in time-varying channel and circuit conditions. Robust adaptation algorithms suitable for discrete-time (DT)...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.