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A floorplanning has a potential to reduce chip temperature due to the conductive nature of heat. If floorplan optimization, which is usually based on simulated annealing, is employed to reduce temperature, its evaluation should be done extremely fast with high accuracy. A new thermal index, named thermal signature, is proposed. It approximates the temperature calculation, which is done by taking the...
Time budgeting, which assigns timing assertion at block boundary, is a crucial step in hierarchical design. The proportion of high- and low-Vt gates of each block, which determines overall leakage power consumption, is dictated by timing assertion, yet dual-Vt allocation is not taken into account during conventional time budgeting. Bounded potential slack is introduced as a measure of dual-Vt allocation,...
Timing yield, in conjunction with other types of yield, directly affects profit; under-estimation is as bad as over-estimation, because large amount of time is unnecessarily spent to increase small amount of timing yield. The correlation that stems from clock network, when ignored, turns out to be one of the reasons of under-estimation in clocked sequential circuit. Three sources of topological correlation...
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