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Hardware Trojan detection has been the subject of many studies in the realm of hardware security in the recent years. The effectiveness of current techniques proposed for Trojan detection is limited by some factors, process variation noise being a major one. This paper introduces latch-based structures as a self-reference detection technique which uses in-circuit path delays as golden reference models...
In this paper we present a novel method for real time hardware implementation of Central Pattern Generators (CPGs) for bipedal robot walking. We introduce a closed form solution for Matsuoka CPG model which is a widely applied parametric neuron-based method for walking pattern generation. Existing parameter tuning methods including trial and error, optimization methods like genetic algorithms or etc...
In today's competitive market, intellectual property (IP) protection plays an important role in the EDA industry because of lots of money invested in designing these cores. Protecting soft IPs is much more challenging because it can be easily copied and even be sold at lower levels of abstraction. In this paper, a new active protecting approach is proposed. Using the sequence of states in the host...
In one-way quantum computation (1WQC) model, an initial highly entangled state called a graph state is used to perform universal quantum computations by a sequence of adaptive single-qubit measurements and post-measurement Pauli-X and Pauli-Z corrections. The needed computations are organized as measurement patterns or simply patterns in the 1WQC model. The entanglement operations in a pattern can...
In the one-way quantum computation (1WQC) model, computations are done by correlated sequences of entanglement, measurement and local corrections commands. As scalable and reliable quantum computers have not been implemented yet, the only widely available tools for designing and testing quantum algorithms are quantum computation simulators. However, simulating quantum computations on a standard classical...
Hardware Trojan horses (HTHs) are important threats to the trustworthiness of hardware chips. Design-forhardware-trust (DFHT) techniques are used to enhance the detectability of possible HTHs. Existing DFHT approaches are usually ad-hoc techniques. This characteristic makes them vulnerable to neutralization efforts. We study this concept by focusing on an effective available DFHT technique, namely...
Fault tolerance is a necessity for successful realization of quantum circuits. Achieving fault tolerance in quantum circuits is more complicated than classic circuits due to their inherent characteristics such as error continuum, destruction of quantum state after measurement, and no-cloning. Adding fault tolerance should incur a reasonably minimal overhead in latency and area. In this paper, a new...
Quantum circuit design flow consists of two main tasks: synthesis and physical design. Synthesis converts the design description into a technology-dependent netlist and then, physical design takes the fixed netlist, produces the layout, and schedules the netlist on the layout. Quantum physical design problem is intractable. This process can be divided into two main processes: scheduling and layout...
Comparing three-dimensional structure of proteins is one of the most fundamental problems in bioinformatics. In recent years, various algorithms have been proposed to solve this problem efficiently. The proposed algorithms are very time-consuming due to high complexity and large input data. In this paper, hardware acceleration is applied to minimize the execution time of a previous algorithm, called...
In one-way quantum computation (1WQC) model, universal quantum computations are performed using measurements to designated qubits in a highly entangled state. The choices of basis for these measurements as well as the structure of the entanglements specify a quantum algorithm. Although a number of methods have been proposed to simulate quantum circuit model on classical computers, no efficient tool...
In one-way quantum computations (1WQC), quantum correlations in an entangled state, called a cluster or graph state, are exploited to perform universal quantum computations using single-qubit measurements. The choices of bases for these measurements as well as the structure of the entanglements specify a quantum algorithm. The needed computations in this model are organized as patterns. Previously,...
One of the major challenges in the process of three-dimensional integrated circuit fabrication is the manufacturing of through silicon vias (TSV). These TSVs compared with other connection elements require high manufacturing costs as well as large silicon area. In this paper, replication technique has been used to reduce the number of TSVs in 3D FPGAs. Replication is implemented for circuit input...
In high frequency FPGAs with technology scale shrinking and threshold voltage value decreasing and based on existing large numbers of unused resources, leakage power has a considerable contribution in total power consumption. On the other hand, process variation, as an important challenge in nano-scale technologies, has a great impact on leakage power of FPGAs. Reconfigurability of FPGAs makes an...
Leakage power in nano-scale technologies is an important source of power consumption. Moreover, FP-GAs with low utilization rates consume large leakage power in their routing and logical resources. As FPGA routing architecture incorporates large number of transistors, leakage power of routing resources contributes the majority of total leakage power consumption. In this paper, a pre-routing prediction...
SRAM-based FPGAs suffer from soft errors caused by cosmic particles. This paper introduces a new switch box architecture to mitigate soft errors. In this switch box architecture, the number of SRAM bits required for programming the switch boxes is reduced by means of switch reduction with slight impact on routing capability of the switch box. This architecture does not require any modification of...
Mis-prediction is a dominant problem in nano-scale design that may diminish the quality of physical design algorithms or may even result in failing the design cycle convergence. In this paper, a new planning methodology is presented in which a masterplan of the chip is constructed in early levels of physical design and the rest of succeeding physical design stags operate considering this masterplan...
In recent years, parameter variations present critical challenges for manufacturability and yield on integrated circuits. In this paper, a new method for improving the timing yield of field programmable gate array (FPGA) devices affected by random and systematic within-die variation is proposed. By selection of an appropriate configuration from a set of functionally equivalent configurations average...
Reversible logic has applications in various research areas including low-power design and quantum computation. In this paper, a rule-based optimization approach for reversible circuits is proposed which uses both negative and positive control Toffoli gates during the optimization. To this end, a set of rules for removing NOT gates and optimizing sub-circuits with common-target gates are proposed...
This paper proposes a new switch box architecture in SRAM-based FPGAs to mitigate soft error effects. In this switch box architecture, the number of SRAM bits required for programming switch box is reduced to 67% without any impact on routing capability of the switch box. This architecture does not require any modification of the existing placement and routing algorithms. The architecture was evaluated...
Replacing functional units of an extensible processor with reconfigurable fnctional units enhances performance and flexibility ofprocessors to execute custom instructions. That is due to the ability ofreconfigurable fnctional units to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this paper, we develop a heterogeneous architecture...
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