The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A low noise, 250-MHz fifth order 0.1 dB ripple chebyshev Gm-C filter, with a discrete tuning scheme in 0.18-μm CMOS is presented. The tuning circuit employs an amplitude locked loop (ALL) to find the correct tuning word to maintain fc within 250MHz ±5% for VDD variation of 1.8±0.1V, temperature variation of −40°C to 125°C and across process corners. Compared to conventional tuning schemes, proposed...
A 20-GHz voltage-controlled oscillator (VCO) for phase-locked loop (PLL) synthesizer is presented in this paper. The VCO and PLL synthesizer have been implemented using only CMOS devices of a 0.13-μπι SiGe BiCMOS technology with the chip area of 0.22 mm2 and 0.48 mm2, respectively. The measured tuning range of the VCO is 2.21 GHz from 19.9 to 22.11 GHz; the PLL synthesizer can generate output frequencies...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.