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This paper shows how to optimize full custom, fixed coefficient filters to gain both in area and speed. The idea is to trade the filter order with the coefficient length and thus reduce the delay and the size of the multipliers. The result is a smaller design that needs fewer clock cycles per sample compared to a minimum order filter. Measurements on the manufactured chips verified a speed gain of...
This paper presents an analysis on energy dissipation of digital half-band filters operating in the sub-threshold (sub-VT) region with throughput and supply voltage constraints. A 12-bit filter is implemented along with various unfolded structures, used to form a decimation filter chain. The designs are synthesized in a 65 nm low-leakage CMOS technology with various threshold voltages. A sub-VT energy...
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