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Programming models like CUDA, OpenMP, OpenACC and OpenCL are designed to offload compute-intensive workloads to accelerators efficiently. However, the naive offload model, which synchronously copies and executes in sequence, requires extensive hand-tuning of techniques, such as pipelining to overlap computation and communication. Therefore, we propose an easy-to-use, directive-based pipelining extension...
About ten years ago, we presented the results of an effort to identify the "right metric" for efficient supercomputing at this workshop, The Workshop on High-Performance, Power-Aware Computing. In this paper, we review the advances that the community has made in this area of research. The intention of this ten-year retrospective is two-fold: (1) to acknowledge the past work through a historical...
Graphics processing units (GPUs) are becoming increasingly common in today's computing systems due to their superior performance and energy efficiency relative to their cost. To further improve these desired characteristics, researchers have proposed several software and hardware techniques. Evaluation of these proposed techniques could be tricky due to the ad-hoc nature in which applications are...
The increasing demand for computation and the commensurate rise in the power density of data centers have led to increased costs associated with constructing and operating a data center. Exacerbating such costs, data centers are often over-provisioned to avoid costly outages associated with the potential overloading of electrical circuitry. However, such over-provisioning is often unnecessary since...
By scheduling multiple applications with complementary resource requirements on a smaller number of compute nodes, we aim to improve performance, resource utilization, energy consumption, and energy efficiency simultaneously. In addition to our naive consolidation approach, which already achieves the aforementioned goals, we propose a new energy efficiency-aware (EEA) scheduling policy and compare...
In the context of the rapid slowing of Dennard's scaling, we characterize the efficacy of one of the power-management mechanisms, namely concurrency throttling, which adapts the concurrency (i.e., number of active threads per core) of an application via simultaneous multithreading (SMT). SMT can potentially improve the processor utilization and thus the efficiency of the processor for parallel programs...
In recent years, the high-performance computing (HPC) community has recognized the need to design energy-efficient HPC systems. The main focus, however, has been on improving the energy efficiency of computation, resulting in an oversight on the energy efficiencies of other aspects of the system such as memory or disks. Furthermore, the energy consumption of the non-computational parts of a HPC system...
The graphics processing unit (GPU) has made significant strides as an accelerator in parallel computing. However, because the GPU has resided out on PCIe as a discrete device, the performance of GPU applications can be bottlenecked by data transfers between the CPU and GPU over PCIe. Emerging heterogeneous computing architectures that "fuse" the functionality of the CPU and GPU, e.g., AMD...
For decades, performance has been the driving force behind high-performance computing (HPC). However, in recent years, power consumption has become an important constraint as operational costs of a supercomputer are now on par with the acquisition costs of a supercomputer. Even though we face major energy issues in achieving large-scale performance, there is still a lack of a standardized power measurement...
High-performance computing (HPC) has become an indispensable resource in science and engineering, and it has oftentimes been referred to as the "thirdpillar" of science, along with theory and experimentation. Performance tuning is a key aspect in utilizing HPC resources to the fullest extent. However, recent exascale studies suggest that power and energy consumption will be a major impediment...
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