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For the first time, CMOS devices on UTBOX 25nm combined with strained SOI (sSOI) substrates have been demonstrated. A 20% Ion boost is highlighted with these substrates compared to the standard UTBB SOI ones. Performance up to 1530µA/µm @ Ioff=100nA/µm (Vd 1V) for a nominal Lg=30nm with a CET of 1.5nm for the NMOS has been achieved. The viability of this substrate has been demonstrated thanks to our...
Carrier mobility at various back-gate biases is studied for n- and p-channel ultrathin (8 nm) SOI MOSFETs with thin (10 nm) buried oxide (BOX) and ground plane (GP). We found that did not deteriorate for either thin BOX or GP structure, even in the back channel (BC). We also found the largest enhancement effect in p-channel devices by the back-gate bias. As this enhancement effect could...
This paper highlights the interest of FD-SOI with high-k and metal gate as a possible candidate for low power multimedia technology. The possibility of multi-VT by combining UTBOX with back plane, back biasing, variable TiN thickness and Al2O3 in the gate stack is demonstrated. The viability of these approaches is corroborated via mobility and reliability measurements. Dual gate oxide co-integrated...
We demonstrate that planar Fully Depleted Silicon-On-Insulator (FDSOI) architectures allow improving the electrostatic control (and in turn the dynamic performance by 22%) and the variability of Complementary Metal-Oxide-Semiconductors (CMOS) devices, compared to the bulk technology. It is thus an ideal solution for Low Power (LP) applications and SRAM stability at the 22 nm node and below. Moreover,...
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