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While the 3D sequential process is still under development, the electrical influence of specific process for the bottom tier needs to be studied. As another MOS transistor layer is fabricated on top of the bottom one, contamination risk and thermal stability issues appear, thus requiring adaptation of conductors/dielectrics for intermediate Back-End Of Line (iBEOL) processing. As materials differ...
In this paper, a new compact, robust and low leakage 4T SRAM cell is proposed. It is based on an original concept of multi-VT thin buried oxide (BOx) fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs with ground plane (GP) in 45 nm technology node. The stability of the cell reaches 20% of VDD and the cell leakage is 13 pA. A minimum cell area of 0.209 mum2 with specific 45 nm SRAM design rules...
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