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We investigate the effect of offset between source/drain (S/D) and gate electrodes (both top gate (TG) and bottom gate (BG)) on the electrical performance of dual-gate (DG) amorphous indium–gallium–zinc-oxide (a-IGZO) thin-film transistors (TFTs). The performance of the fabricated TFTs measured by BG sweep under various TG potentials are well fitted by TCAD simulation with the same density of states,...
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