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Fabrication of high aspect ratio through silicon vias (TSVs) in a Si interposer and fine pitch solder microbumps on a top Si die is discussed in this paper. Chip stacking result of the Si interposer and the top Si die is also presented. TSVs with 25 in pitch and aspect ratio higher than 10 are etched with BOSCH process. To avoid difficulties in wetting the sidewall of the TSVs, bottom-up...
In order to uniformly expose Cu via, TSV wafer thinning becomes much critical contrary to conventional process. The complete wafer thinning process is expected composed of not only grinding, but also handling. This study develops advance wafer thinning process from temporary carrier bonding to carrier de-bonding that also includes grinding and backside processes. In this case, the bonded wafer thinning...
Since 3D-IC becomes popular nowadays, solder micro-bumps plays an important role to develop TSV technology. This study verifies solder micro-bump efficiency via cracking as index. The micro-bump cracking is observed at the interface of intermetallic compound (IMC) layer after Si chip and Si carrier bonding. It was found that P-rich Ni layer will perform weaker and brittle solder joint by means of...
High density three dimensional (3D) interconnects formed by high aspect ratio through silicon vias (TSVs) and fine pitch solder microbumps are presented in this paper. The aspect ratio of the TSV is larger than 10 and filled with Cu without voids; there are electrical nickel and immersion gold (ENIG) pads on top of the TSV as under bump metallurgy (UBM) layer. On the Si chip, Cu/Sn solder microbumps...
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