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Recently, FPGAs have been widely used in the implementation of hardware accelerators for Convolutional Neural Networks (CNN), especially on mobile and embedded devices. However, most of these existing accelerators are designed with the same concept as their ASIC counterparts, that is all operations from different CNN layers are mapped to the same hardware units and work in a multiplexed way. Although...
Phase detection and behavior analysis have been major concerned to improve the performance as well as the system throughputs. However, for the distributed acceleration engines, the execution among different phases is much more difficult to be analyzed, especially for the loop based programs. With respect to the tasks in different iterations, how to efficiently detect the phases belonging to the same...
A fully digital FPGA-based high count-rate coincidence system has been developed for TOF and non-TOF PET cameras. Using hybrid method combining AND-logic and Time-mark technology can gain both excellent timing resolution and high processing speed. In this hybrid architecture, every gamma event is synchronized by a 125 MHz system clock and generating a trigger associated with a time-mark given by an...
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