The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We present a new 0.35um BCDMOS technology with a capability of 8 to 60V NLDMOS. The proposed process do not need level shifter, charge pump and boost up due to the same gate oxide thickness with logic 5V CMOS. And the Rsp of the proposed 24V NLDMOS structure is lower by 46% than conventional structure. The process has no thermal budget modification but use simple additional implant step. Also it is...
We present a new 0.3 5um BCD technology with a capability of 8 to 60V p-ch LDMOS. The proposed p-ch LDMOS employs the S-PWELL in the p-epi region to ensure high breakdown voltage and low on-resistance. The Rsp of the proposed 60V p-ch LDMOS is lower by 42% than conventional one. And we modified the 300Å gate oxide of the original p-ch LDMOS to 125Å so that the proposed p-ch LDMOS is efficient for...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.