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In this paper, a NOR gate implemented by SOI technique that eliminates power dissipation by reducing the number of parallel transistors is presented. This technique is applicable in each circuit which has parallel transistors. It can approximately decrease the area to 50% in high input circuits. In this work, we evaluate and compare the area, power and delay by the HSPICE simulator in 0.25mum CMOS...
In this paper, the performance of double-edge triggered feedbacked flip-flop (DFFF) in SOI and bulk technologies has been compared. DFFF power consumption is reduced by avoiding unnecessary internal node transition. The subthreshold current in this flip-flop is very low compared to the other structures. Reducing the number of transistors in the stack and increasing the number of charge path lead to...
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