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State-of-the-art digital fractional-N PLLs intended for modern wireless systems make use of high-resolution and high-linearity time-to-digital converters (TDCs) in order to meet the stringent integral phase noise requirements. Those high-performance TDCs complicate the synthesizer design and dissipate large part of the power budget, leading to poor jitter-power compromise. This paper introduces a...
The resynchronization of a frequency divider output is routinely used in the design of low-noise phase-locked loops (PLLs) in order to remove additional phase noise and avoid modulus-dependent nonlinearity. However, metastability issues cause PLLs to fail to lock or to degrade jitter at certain synthesized frequencies. This brief proposes a novel automatic retiming circuit, which mitigates metastability...
This paper reports a multi-channel neural recording system-on-chip (SoC) with digital data compression and wireless telemetry. The circuit consists of a 16 amplifiers, an analog time division multiplexer, an 8-bit SAR AD converter, a digital signal processor (DSP) and a wireless narrowband 400-MHz binary FSK transmitter. Even though only 16 amplifiers are present in our current die version, the whole...
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