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Evaluating the resilience of a given circuit against adverse effects, such as radiation-induced single event upsets, is a complex and frequently time-demanding task. For Field Programmable Gate Arrays (FPGAs), this task has the additional complexity of accounting for faults affecting the configuration memory. For this reason, several works propose techniques to inject and evaluate faults affecting...
Providing high reliability for FPGAs is a demanding task, as such devices may be subject to faults in the configuration bitstream, altering the specified function. Traditional modular redundancy remains the most used technique, due to its high fault coverage and low performance overhead. When high availability and strict real-time deadlines must be considered, however, a short mean time to repair...
Possible scenarios for future manufacturing technologies increase the desirable features of fault tolerance techniques, such as coping with multiple faults and reducing error latency. On the other hand, current high-end FPGAs present, besides lookup tables and flip-flops, several dedicated components that perform the most commonly required functions. In this paper, we propose an approach to use such...
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