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This paper presents an ATPG framework for IDDQ testing of both intra- and inter-gate bridging faults. The framework integrates random simulation and a deterministic stage using Boolean SATisfiability (SAT) as the underlying engine. This decides whether a fault is testable or untestable. In this way, we conduct an exact search for test patterns for IDDQ testing of both intra- and inter-gate bridging...
This paper presents an exact method which finds the minimum factored form of an incompletely specified Boolean function. The problem is formulated as a quantified Boolean formula (QBF) and is solved by general-purpose QBF solver. We also propose a novel graph structure, called an X-B (exchanger binary) tree, which implicitly enumerates binary trees. Using this graph structure, the factoring problem...
This paper presents a new dual-rail PLA with 2-input logic cells. The 2-input logic cells composed of pass-transistors can realize any 2-input Boolean function and are embedded in a dual-rail PLA without degradation of circuit performance. By using the logic cells, some classes of logic function can be implemented in a smaller circuit area, so that a high-speed and low-power operation is also achieved...
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