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Pre-emphasis is often employed at the transmitter side to counteract the inter symbol interface (ISI) in high-speed data communications. Traditional pre-emphasis drivers, implemented in CML, use one pair of CMOS transistors as the output stage. To design a pre-emphasis for different channels or the same channel using different type of equalizer requires a wide range of current for the same tap. The...
A 1 V supply 1:2 demultiplexer (DEMUX) based on 0.13 mum CMOS technology is presented. It is designed for 40-Gb/s optical communication systems. This DEMUX achieved by a pair of master-slave flip-flops (MS-FFs) with opposite clock can operate at 40-Gb/s and beyond. Fully differential current mode logic (CML) is adopted to improve the bit rate of non-return-to-zero (NRZ) data stream and to suppress...
In this paper, a low supply static 2:1 frequency divider based on 0.13 mum CMOS is presented. It is designed for 40-Gb/s optical communication systems. Current-mode logic (CML) is adopted because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. This frequency divider is designed with output buffer to drive the external 50 Omega loads. On-chip shunt peaking...
A finite impulse response (FIR) 6-tap pre-emphasis (PEP) filter with programmable coefficients was employed to counteract intersymbol interface (ISI) in high speed backplane data communication or optical communication. The proposed circuit can operate at the data rates up to 10 Gb/s. This circuit is designed in 90 nm CMOS technology and operates at 1.0 V. Simulation results show that the circuit improves...
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